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ISL9N2357D3ST
Data Sheet June 2002
30V, 0.007 Ohm, 35A, N-Channel UltraFET(R) Trench Power MOSFET
UltraFET(R) Trench from Fairchild is a new advanced MOSFET technology that achieves the lowest possible onresistance per silicon area while maintaining fast switching and low gate charge. The reduced conduction and switching losses extend battery life in notebook PCs, cellular telephones and other portable information appliances and improve the overall efficiency of high frequency DC-DC converters used to power the latest microprocessors.
UltraFET(R) Trench
Features
* rDS(ON) = 0.006 Typical, VGS = 10V * Qg Total 85nC Typical, VGS = 10V * Qgd 16nC Typical * CISS 5600pF Typical
Packaging
ISL9N2357D3ST JEDEC TO-252AA
DRAIN (FLANGE)
Symbol
D
G
GATE SOURCE
S
Ordering Information
PART NUMBER ISL9N2357D3ST PACKAGE TO-252AA BRAND N2357D
NOTE: When ordering, use the entire part number. e.g., ISL9N2357D3ST.
Absolute Maximum Ratings
SYMBOL VDSS VDGR VGS ID ID IDM PD TJ, TSTG TL Tpkg RJC RJA NOTE: 1. TJ = 25oC to 150oC.
TC = 25oC, Unless Otherwise Specified PARAMETER ISL9N2357D3ST 30 30 20 35 35 Figure 4 100 0.67 -55 to 175 300 260 UNITS V V V A A A W W/oC
oC oC oC
Drain to Source Voltage (Note 1) Drain to Gate Voltage (RGS = 20k) (Note 1) Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2) Continuous (TC = 100oC, VGS = 10V) Pulsed Drain Current Power Dissipation Derate Above 25oC Operating and Storage Temperature Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s Package Body for 10s, See Techbrief TB334
THERMAL SPECIFICATIONS Thermal Resistance Junction to Case, TO-252 Thermal Resistance Junction to Ambient TO-252 1.5 100
oC/W oC/W
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
(c)2002 Fairchild Semiconductor Corporation
ISL9N2357D3ST Rev. B1
ISL9N2357D3ST
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 9) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source ON Resistance VGS(TH) rDS(ON) VGS = VDS, ID = 250A (Figure 8) ID = 35A, VGS = 10V (Figure 7) 2 0.006 4 0.007 V IGSS VGS = 20V 30 1 250 100 V A A nA TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge at 20V Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 10) 5600 526 355 pF pF pF Qg(TOT) Qg(10) Qg(TH) Qgs Qgd VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 15V, ID = 20A, Ig(REF) = 1.0mA (Figures 11, 12, 13) 172 85 11 23 16 258 130 17 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID = 20A VGS = 10V, RGS = 9.1 (Figures 14, 15) 27 69 84 53 144 207 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 20A ISD = 10A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 20A, dISD/dt = 100A/s ISD = 20A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.0 34 29 UNITS V V ns nC
(c)2002 Fairchild Semiconductor Corporation
ISL9N2357D3ST Rev. B1
ISL9N2357D3ST Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 40
ID, DRAIN CURRENT (A) 2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
30
20
10
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
THERMAL IMPEDANCE
ZJC, NORMALIZED
PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-4 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
0.01 10-5
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000 1000 IDM, PEAK CURRENT (A)
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 10V 150 - TC 125
100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
10 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
FIGURE 4. PEAK CURRENT CAPABILITY
(c)2002 Fairchild Semiconductor Corporation
ISL9N2357D3ST Rev. B1
ISL9N2357D3ST Typical Performance Curves
80 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
(Continued)
80 VGS = 10V ID, DRAIN CURRENT (A) 60 VGS = 6V VGS = 5V 40 VGS = 7V
ID , DRAIN CURRENT (A)
60
40
TJ = 175oC
20 TJ = 25oC TJ = -55oC 0 2 3 4 5 6 VGS , GATE TO SOURCE VOLTAGE (V)
20
TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 .5 1 1.5 2
0 VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. TRANSFER CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS
1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE
1.2 VGS = VDS, ID = 250A
1.4 1.0
1.2
0.8
1.0
0.8 VGS = 10V, ID = 20A 0.6 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
0.6
0.4 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A
10000 CISS = CGS + CGD
1.1
C, CAPACITANCE (pF)
COSS CDS + CGD 1000 CRSS = CGD
1.0
0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC)
100 0.1
VGS = 0V, f = 1MHz 1 10 30
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
(c)2002 Fairchild Semiconductor Corporation
ISL9N2357D3ST Rev. B1
ISL9N2357D3ST Typical Performance Curves
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 15V 8
(Continued)
6
4
2
WAVEFORMS IN DESCENDING ORDER: ID = 35A ID = 20A ID = 5A 0 20 40 60 80 100
0 Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 11. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 10V
DUT Ig(REF)
FIGURE 12. GATE CHARGE TEST CIRCUIT
FIGURE 13. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10% 90%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH 50%
FIGURE 14. SWITCHING TIME TEST CIRCUIT
FIGURE 15. SWITCHING TIME WAVEFORM
(c)2002 Fairchild Semiconductor Corporation
ISL9N2357D3ST Rev. B1
ISL9N2357D3ST PSPICE Electrical Model
.SUBCKT ISL9N2357 2 1 3 ;
CA 12 8 2.5e-9 CB 15 14 2.1e-9 CIN 6 8 5.2e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
10
rev Aug 2000
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
ESG 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 4.3e-9 LSOURCE 3 7 1.6e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.8e-3 RGATE 9 20 1.68 RLDRAIN 2 5 10 RLGATE 1 9 43 RLSOURCE 3 7 16 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.8e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*550),3))} .MODEL DBODYMOD D (IS = 1.01e-12 RS = 3.5e-3 ikf = 15 TRS1 = 1.01e-3 TRS2 = 1.21e-6 CJO = 6.8e-10 TT = 6.7e-9 M = 0.35) .MODEL DBREAKMOD D (RS = 0.068 TRS1 = 1.12e-3 TRS2 = 1.25e-6) .MODEL DPLCAPMOD D (CJO = 8.5e-10 IS = 1e-30 N = 10 M = 0.31) .MODEL MMEDMOD NMOS (VTO = 3.5 KP = 6.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.68) .MODEL MSTROMOD NMOS (VTO = 4.1 KP = 110 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 3.0 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 16.8 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.01e-3 TC2 = 1.07e-7) .MODEL RDRAINMOD RES (TC1 = 4.5e-3 TC2 = 8.0e-6) .MODEL RSLCMOD RES (TC1 = 1.02e-4 TC2 = -1.13e-6) .MODEL RSOURCEMOD RES (TC1 = 1.0e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -3.0e-3 TC2 = -1.5e-5) .MODEL RVTEMPMOD RES (TC1 = -4.0e-3 TC2 = 1.25e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.0 VOFF= -1.5) VON = -1.5 VOFF= -6.0) VON = -0.7 VOFF= 0) VON = 0 VOFF= -0.7)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2002 Fairchild Semiconductor Corporation
+
-
EBREAK 11 7 17 18 33.39 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
RDRAIN 21 16
-
VBAT +
8 22 RVTHRES
ISL9N2357D3ST Rev. B1
ISL9N2357D3ST SABER Electrical Model
REV Aug 2000 template ISL9N2357 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 1.01e-12, rs = 3.5e-3, ikf=15, trs1 = 1.01e-3, trs2 = 1.21e-6, cjo = 6.8e-10, tt = 6.7e-9, m = 0.35) dp..model dbreakmod = (rs = 0.068, trs1 = 1.12e-3, trs2 = 1.25e-6) dp..model dplcapmod = (cjo = 8.5e-10, isl = 10e-30, nl=10, m = 0..31) m..model mmedmod = (type=_n, vto = 3.5, kp = 6.0, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 4.1, kp = 110, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 3.0, kp = 0.03, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.0, voff = -1.5) DPLCAP 5 sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -6.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.7, voff = 0) 10 sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.7) c.ca n12 n8 = 2.5e-9 c.cb n15 n14 = 2.1e-9 c.cin n6 n8 = 5.5e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 4.3e-9 l.lsource n3 n7 = 1.6e-9
GATE 1 RLGATE CIN LGATE RSLC1 51 RSLC2 ISCL
LDRAIN DRAIN 2 RLDRAIN
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBREAK 11 DBODY MWEAK MMED EBREAK + 17 18
MSTRO 8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.01e-3, tc2 = 1.07e-7 res.rdrain n50 n16 = 2.8e-3, tc1 = 4.5e-3, tc2 = 8.0e-6 res.rgate n9 n20 = 1.68 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 43 res.rlsource n3 n7 = 16 res.rslc1 n5 n51= 1e-6, tc1 = 1.02e-4, tc2 = -1.13e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.8e-3, tc1 = 1.0e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -4.0e-3, tc2 = 1.25e-6 res.rvthres n22 n8 = 1, tc1 = -3.0e-3, tc2 = -1.5e-5 spe.ebreak n11 n7 n17 n18 = 33.39 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/550))** 3)) } }
S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B
RSOURCE
LSOURCE 7 RLSOURCE
SOURCE 3
15
RBREAK 17 18 RVTEMP
CB + EDS 5 8
19 14 IT
VBAT +
-
-
8 RVTHRES
22
(c)2002 Fairchild Semiconductor Corporation
ISL9N2357D3ST Rev. B1
ISL9N2357D3ST SPICE Thermal Model
REV 23March 2000 ISL9N2357T CTHERM1 th 6 3.0e-3 CTHERM2 6 5 4.0e-3 CTHERM3 5 4 4.8e-3 CTHERM4 4 3 5.2e-3 CTHERM5 3 2 8.5e-3 CTHERM6 2 tl 5.0e-2 RTHERM1 th 6 3.5e-3 RTHERM2 6 5 8.5e-3 RTHERM3 5 4 5.7e-2 RTHERM4 4 3 2.5e-1 RTHERM5 3 2 4.3e-1 RTHERM6 2 tl 4.5e-1
th JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model ISL9N2357T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 3.0e-3 ctherm.ctherm2 6 5 = 4.0e-3 ctherm.ctherm3 5 4 = 4.8e-3 ctherm.ctherm4 4 3 = 5.2e-3 ctherm.ctherm5 3 2 = 8.5e-3 ctherm.ctherm6 2 tl = 5.0e-2 rtherm.rtherm1 th 6 = 3.5e-3 rtherm.rtherm2 6 5 = 8.5e-3 rtherm.rtherm3 5 4 = 5.7e-2 rtherm.rtherm4 4 3 = 2.5e-1 rtherm.rtherm5 3 2 = 4.3e-1 rtherm.rtherm6 2 tl = 4.5e-1 }
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2002 Fairchild Semiconductor Corporation
ISL9N2357D3ST Rev. B1
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx Bottomless CoolFET CROSSVOLT DenseTrench DOME EcoSPARK E2CMOSTM EnSignaTM FACT FACT Quiet Series
DISCLAIMER
FAST a FASTr FRFET GlobalOptoisolator GTO HiSeC I2C ISOPLANAR LittleFET MicroFET MicroPak
MICROWIRE OPTOLOGIC a OPTOPLANAR PACMAN POP Power247 PowerTrench a QFET QS QT Optoelectronics Quiet Series
SILENT SWITCHER a UHC SMART START UltraFET a SPM VCX STAR*POWER Stealth SuperSOT-3 SuperSOT-6 SuperSOT-8 SyncFET TinyLogic TruTranslation
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. H5

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